Design And Analysis of low Power Memory Elements for high Speed VLSI Circuits

Abstract

For today and for the future technology Power Performance and Area (PPA) newlinewould be the most focused stuff in the memory design. By keeping this in mind newlinewe have started with the low power high speed memory elements. Initially an extremely low power true 1and#8722;and#981; clocking flip-flop is proposed using eighteen transistors newlineonly. The flip-flop is a synchronous bistable element that stores single-bit information. To design this Master Slave (MS) type architecture, topological, logical, and newlineadaptive coupling techniques are employed. The minimum number of transistors newlineare maintained by using above techniques, which comprises of complementary pass newlinetransistor logic and static complementary MOS logic. It also offers low power, a low newlinedelay that speeds up the flip-flops, and low complexity by reducing the transistor newlinecount. The proposed hybrid logic architecture has showed the highest percentage newlinei.e. 49.73% improvement in terms of power as compared to LRFF newline