Design and synthesis of efficient MAC architectures for high speed decimal processor

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dc.contributor.guideJacob, K Pouloseen_US
dc.coverage.spatialComputer Sciencesen_US
dc.creator.researcherJames, Rekha Ken_US
dc.date.accessioned2013-05-07T10:53:12Z
dc.date.available2013-05-07T10:53:12Z
dc.date.awarded2010en_US
dc.date.completed04/01/2010en_US
dc.date.issued2013-05-07
dc.date.registeredn.d.en_US
dc.description.noteAppendix and List of publications included, References p. 213-224en_US
dc.format.accompanyingmaterialNoneen_US
dc.format.dimensions--en_US
dc.format.extent224p.en_US
dc.identifier.urihttp://hdl.handle.net/10603/8623
dc.languageEnglishen_US
dc.publisher.institutionDepartment of Computer Scienceen_US
dc.publisher.placeCochinen_US
dc.publisher.universityCochin University of Science and Technologyen_US
dc.relationNo. of references 109en_US
dc.rightsuniversityen_US
dc.source.inflibnetINFLIBNETen_US
dc.subject.keywordComputer Sciencesen_US
dc.subject.keywordHigh speed decimal processoren_US
dc.titleDesign and synthesis of efficient MAC architectures for high speed decimal processoren_US
dc.title.alternativeen_US
dc.type.degreePh.D.en_US

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