Enhanced DFT Methodologies for Improvement In Test Coverage And Yield In Finfet Circuits

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dc.contributor.guideSivanantham S
dc.coverage.spatial
dc.creator.researcherRenold Sam Vethamuthu .E
dc.date.accessioned2024-10-11T09:49:39Z
dc.date.available2024-10-11T09:49:39Z
dc.date.awarded2024
dc.date.completed2024
dc.date.registered2017
dc.description.abstractnewline
dc.description.note
dc.format.accompanyingmaterialNone
dc.format.dimensions
dc.format.extent1-128
dc.identifier.urihttp://hdl.handle.net/10603/594798
dc.languageEnglish
dc.publisher.institutionSchool of Electronic Engineering
dc.publisher.placeVellore
dc.publisher.universityVellore Institute of Technology, Vellore
dc.relation
dc.rightsuniversity
dc.source.universityUniversity
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering Electrical and Electronic
dc.titleEnhanced DFT Methodologies for Improvement In Test Coverage And Yield In Finfet Circuits
dc.title.alternative
dc.type.degreePh.D.

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