Low Power High Speed Resilient Architectures for High Sensitive Arithmetic Circuits Using Machine Learning Algorithms for Accuracy Analysis

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dc.contributor.guideS Koteswara Rao and JVR Ravindra
dc.coverage.spatial
dc.creator.researcherLavanya Maddisetti
dc.date.accessioned2023-05-17T05:32:29Z
dc.date.available2023-05-17T05:32:29Z
dc.date.awarded2023
dc.date.completed2023
dc.date.registered2015
dc.description.abstractnewline
dc.description.note
dc.format.accompanyingmaterialDVD
dc.format.dimensions
dc.format.extent
dc.identifier.urihttp://hdl.handle.net/10603/483751
dc.languageEnglish
dc.publisher.institutionDepartment of Electronics and Communication Engineering
dc.publisher.placeVaddeswaram
dc.publisher.universityKoneru Lakshmaiah Education Foundation
dc.relation
dc.rightsuniversity
dc.source.universityUniversity
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering Electrical and Electronic
dc.titleLow Power High Speed Resilient Architectures for High Sensitive Arithmetic Circuits Using Machine Learning Algorithms for Accuracy Analysis
dc.title.alternative
dc.type.degreePh.D.

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