Investigations on Low Power Design for Testability Architectures for System on Chip Platforms using Dynamic Scan

dc.contributor.guide	Jackuline Moni D
dc.coverage.spatial
dc.creator.researcher	John Bedford Solomon
dc.date.accessioned	2021-02-17T12:05:18Z
dc.date.available	2021-02-17T12:05:18Z
dc.date.awarded	2020
dc.date.completed	2018
dc.date.registered	2009
dc.description.abstract	newline
dc.description.note
dc.format.accompanyingmaterial	DVD
dc.format.dimensions	A4
dc.format.extent	145 Pages
dc.identifier.uri	http://hdl.handle.net/10603/315620
dc.language	English
dc.publisher.institution	Department of Electronics and Communication Engineering
dc.publisher.place	Coimbatore
dc.publisher.university	Karunya University
dc.relation
dc.rights	university
dc.source.university	University
dc.subject.keyword	Engineering
dc.subject.keyword	Engineering and Technology
dc.subject.keyword	Engineering Electrical and Electronic
dc.title	Investigations on Low Power Design for Testability Architectures for System on Chip Platforms using Dynamic Scan
dc.title.alternative
dc.type.degree	Ph.D.