Low Leakage Variability Aware Techniques for CMOS Logic Circuits

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dc.contributor.guidePattanaik, Manisha
dc.coverage.spatial
dc.creator.researcherSharma, Vijay Kumar
dc.date.accessioned2023-11-20T11:58:37Z
dc.date.available2023-11-20T11:58:37Z
dc.date.awarded2015
dc.date.completed2015
dc.date.registered2011
dc.description.abstractAttached
dc.description.note
dc.format.accompanyingmaterialNone
dc.format.dimensions27.5X21.2
dc.format.extentxxii,205p.
dc.identifier.urihttp://hdl.handle.net/10603/526542
dc.languageEnglish
dc.publisher.institutionDepartment of Electrical and Electronics Engineering
dc.publisher.placeGwalior
dc.publisher.universityAtal Bihari Vajpayee Indian Institute of Information Technology and Management
dc.relation
dc.rightsuniversity
dc.source.universityUniversity
dc.subject.keywordComputer Science Software Engineering
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.titleLow Leakage Variability Aware Techniques for CMOS Logic Circuits
dc.title.alternative
dc.type.degreePh.D.

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