Performance enhancement of CMOS digital circuits strain engineered asymmetric dual k spacer FinFETs

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dc.contributor.guideVishvakarma, Santosh Kumar
dc.coverage.spatial
dc.creator.researcherMaisagalla Gopal
dc.date.accessioned2023-01-13T04:36:29Z
dc.date.available2023-01-13T04:36:29Z
dc.date.awarded2019
dc.date.completed2019
dc.date.registered2014
dc.description.abstractAvailable newline
dc.description.noteTH200
dc.format.accompanyingmaterialNone
dc.format.dimensions
dc.format.extent92p.
dc.identifier.urihttp://hdl.handle.net/10603/444576
dc.languageEnglish
dc.publisher.institutionDepartment of Electrical Engineering
dc.publisher.placeIndore
dc.publisher.universityIndian Institute of Technology Indore
dc.relation
dc.rightsuniversity
dc.source.universityUniversity
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering Electrical and Electronic
dc.titlePerformance enhancement of CMOS digital circuits strain engineered asymmetric dual k spacer FinFETs
dc.title.alternative
dc.type.degreePh.D.

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