Performance enhancement of CMOS digital circuits strain engineered asymmetric dual k spacer FinFETs

Thumbnail Image

Files

01_title.pdf (90.93 KB)
 02_prelim pages.pdf (237.67 KB)
 03_contents.pdf (143.36 KB)
 04_abstract.pdf (100.97 KB)
 05_chapter 1.pdf (708.5 KB)

Date

item.page.authors

Journal Title

Journal ISSN

Volume Title

Publisher

Abstract

Available newline

Description

Keywords

Citation

URI

http://hdl.handle.net/10603/444576

Collections

Department of Electrical Engineering

item.page.endorsement

item.page.review

item.page.supplemented

item.page.referenced