Certain investigations on heuristic optimization techniques for area minimization in fixed outline non slicing voltage island based VLSI floorplanning

dc.contributor.guide	Jayanthi, K B
dc.coverage.spatial	Information and Communication Engineering
dc.creator.researcher	K, Sivasubramanian
dc.date.accessioned	2018-03-15T11:33:56Z
dc.date.available	2018-03-15T11:33:56Z
dc.date.awarded	n.d.
dc.date.completed	2017
dc.date.registered	n.d.
dc.description.abstract	Abstract available
dc.description.note	Data not available
dc.format.accompanyingmaterial	None
dc.format.dimensions	8cm.
dc.format.extent	xxii, 149p.
dc.identifier.uri	http://hdl.handle.net/10603/195986
dc.language	Others
dc.publisher.institution	Faculty of Information and Communication Engineering
dc.publisher.place	Chennai
dc.publisher.university	Anna University
dc.relation	136-148
dc.rights	university
dc.source.university	University
dc.subject.keyword	Floorplanning
dc.subject.keyword	Harmony
dc.subject.keyword	Heuristic
dc.subject.keyword	Slicing
dc.subject.keyword	Swarm
dc.title	Certain investigations on heuristic optimization techniques for area minimization in fixed outline non slicing voltage island based VLSI floorplanning
dc.title.alternative
dc.type.degree	Ph.D.