Development of an algorithm using evolutionary approach for digital circuit layout based on graph partitioning technique

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dc.contributor.guideSingh, Kawaljeeten_US
dc.coverage.spatialComputer Scienceen_US
dc.creator.researcherKaur, Maninderen_US
dc.date.accessioned2015-03-10T11:50:56Z
dc.date.available2015-03-10T11:50:56Z
dc.date.awardedn.d.en_US
dc.date.completed2013en_US
dc.date.issued2015-03-10
dc.date.registeredn.d.en_US
dc.description.abstractAbstract avalibleen_US
dc.description.noteBibliography p.167 - 189en_US
dc.format.accompanyingmaterialNoneen_US
dc.format.dimensions-en_US
dc.format.extent189p.en_US
dc.identifier.urihttp://hdl.handle.net/10603/36772
dc.languageEnglishen_US
dc.publisher.institutionDepartment of Computer Scienceen_US
dc.publisher.placePatialaen_US
dc.publisher.universityPunjabi Universityen_US
dc.relation-en_US
dc.rightsuniversityen_US
dc.source.inflibnetINFLIBNETen_US
dc.subject.keywordalgorithmen_US
dc.subject.keywordapproachen_US
dc.subject.keywordevolutionaryen_US
dc.titleDevelopment of an algorithm using evolutionary approach for digital circuit layout based on graph partitioning techniqueen_US
dc.title.alternative-en_US
dc.type.degreePh.D.en_US

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