Development of an algorithm using evolutionary approach for digital circuit layout based on graph partitioning technique

Thumbnail Image

Files

01_titel.pdf (103.04 KB)
 02_certificate.pdf (165.53 KB)
 03_decelaration.pdf (83.7 KB)
 04_aknowledgement.pdf (89.89 KB)
 05_abstract.pdf (72.34 KB)

Date

2015-03-10

item.page.authors

Journal Title

Journal ISSN

Volume Title

Publisher

Abstract

Abstract avalible

Description

Keywords

Citation

URI

http://hdl.handle.net/10603/36772

Collections

Department of Computer Science

item.page.endorsement

item.page.review

item.page.supplemented

item.page.referenced