Gate sizing for Energy Efficient and Secure Digital Design

dc.contributor.guide	Kamakoti Veezhinathan
dc.coverage.spatial
dc.creator.researcher	Patanjali SLPSK
dc.date.accessioned	2022-10-06T09:05:18Z
dc.date.available	2022-10-06T09:05:18Z
dc.date.awarded	2020
dc.date.completed	2019
dc.date.registered	2011
dc.description.abstract	AVAILABLE newline
dc.description.note
dc.format.accompanyingmaterial	None
dc.format.dimensions
dc.format.extent	xx,97 p
dc.identifier.uri	http://hdl.handle.net/10603/410305
dc.language	English
dc.publisher.institution	Computer Science and Engineering
dc.publisher.place	Chennai
dc.publisher.university	Indian Institute of Technology Madras
dc.relation	65
dc.rights	university
dc.source.university	University
dc.subject.keyword	Computer Science
dc.subject.keyword	Computer Science Software Engineering
dc.subject.keyword	Engineering and Technology
dc.title	Gate sizing for Energy Efficient and Secure Digital Design
dc.title.alternative
dc.type.degree	Ph.D.