FPGA implementation of an efficient Novel viterbi decoder architecture For wireless application

Abstract

Convolutional coding is a coding scheme often employed in deep newlinespace communications and recently in digital wireless communications newlineViterbi decoders are used to decode convolutional codes Viterbi decoders newlineemployed in digital wireless communications are complex and dissipate large newlinepower With the proliferation of battery powered devices such as cellular newlinephones and laptop computers, power dissipation along with speed and area is newlinea major concern in VLSI design newlineThis thesis represents the research work of developing new newlineapproaches for implementing Viterbi decoder designs to minimize probability newlineof error memory utilization power consumption and latency increase newlinethroughput This work examines the decoding process of the Viterbi newlinealgorithm the architecture of the Viterbi decoder and the implementations of newlinethe basic functions This enables the design problems to be discovered Then a newlinevariety of low power design techniques are described and applied to the newlinedecoder design to improve its power efficiency newlineThe first approach presents the implementation of a new nonpolynomial newlineapproach to reduce probability of error of Viterbi decoder newline newline