Analysis and Performance Optimization of Tunnel FETs for Low Power Sensors Design

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dc.contributor.guideKar, R. and Mandal, D.
dc.coverage.spatial
dc.creator.researcherSingh, Navaneet Kumar
dc.date.accessioned2025-03-27T11:13:36Z
dc.date.available2025-03-27T11:13:36Z
dc.date.awarded2024
dc.date.completed2024
dc.date.registered2020
dc.description.abstractnewline
dc.description.note
dc.format.accompanyingmaterialDVD
dc.format.dimensions
dc.format.extent
dc.identifier.researcherid
dc.identifier.urihttp://hdl.handle.net/10603/630389
dc.languageEnglish
dc.publisher.institutionElectronics and Communication Engineering
dc.publisher.placeDurgapur
dc.publisher.universityNational Institute of Technology Durgapur
dc.relation
dc.rightsuniversity
dc.source.universityUniversity
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering Electrical and Electronic
dc.titleAnalysis and Performance Optimization of Tunnel FETs for Low Power Sensors Design
dc.title.alternative
dc.type.degreePh.D.

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