High performance architectures for adaptive equalizers using distributed arithmetic
| dc.contributor.guide | Ahamed, Shaik Rafi | |
| dc.coverage.spatial | Electronics and Electrical Engineering | |
| dc.creator.researcher | Matcha, Surya Prakash | |
| dc.date.accessioned | 2023-05-02T11:08:45Z | |
| dc.date.available | 2023-05-02T11:08:45Z | |
| dc.date.awarded | 2016 | |
| dc.date.completed | 2016 | |
| dc.date.registered | 2009 | |
| dc.description.abstract | In communications adaptive decision feedback equalizers ADFEs are an effective means of countering the intersymbol interference ISI introduced by the channel and also to keep track on the changes in the channel characteristics However high speed applications demand for a large number of taps in the feed forward filter FFF and feedback filter FBF of ADFE and hence the implementation and real time operation of such an equalizer becomes difficult due to increased complexity and very smal | |
| dc.description.note | Not Available | |
| dc.format.accompanyingmaterial | None | |
| dc.format.dimensions | Not Available | |
| dc.format.extent | Not Available | |
| dc.identifier.uri | http://hdl.handle.net/10603/480761 | |
| dc.language | English | |
| dc.publisher.institution | DEPARTMENT OF ELECTRONICS AND ELECTRICAL ENGINEERING | |
| dc.publisher.place | Guwahati | |
| dc.publisher.university | Indian Institute of Technology Guwahati | |
| dc.relation | Not Available | |
| dc.rights | self | |
| dc.source.university | University | |
| dc.subject.keyword | Engineering | |
| dc.subject.keyword | Engineering and Technology | |
| dc.subject.keyword | Engineering Electrical and Electronic | |
| dc.title | High performance architectures for adaptive equalizers using distributed arithmetic | |
| dc.title.alternative | Not available | |
| dc.type.degree | Ph.D. |
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