VLSI Implementation of 2D DCT Image Compression  using Pipelined Architecture

VLSI Implementation of 2D DCT Image Compression using Pipelined Architecture

dc.contributor.guide	Changlani, Soni
dc.coverage.spatial
dc.creator.researcher	Chaturvedi, Prashant
dc.date.accessioned	2023-01-13T12:24:57Z
dc.date.available	2023-01-13T12:24:57Z
dc.date.awarded	2022
dc.date.completed	2021
dc.date.registered	2018
dc.description.abstract	The simulation has been done in Vertex-4. The RTL view is in figure number 8.8.1, newlineRTL schematics view figure number 8.8.2(a), (b),(c), technology schematics view is in newlinefigure number 8.8.3 (a), (b), (c), (d), (e),(f) and design summary is in figure number newline8.8.4, table based on design summary in on table number 8.7 and graphical view for newlinethis summary on figure number 8.8.6. After examine these figures, tables, and format newlineprécis it is concluded that the no. of slices is 7246, no. of flip-flop is 3878, no. of 4 newlineinputs LUT s is 11210 and no. of IOB s is 168. It is also observed that the area newlineutilization is decreased so processor performance has been increased. newline newline
dc.description.note
dc.format.accompanyingmaterial	None
dc.format.dimensions
dc.format.extent
dc.identifier.uri	http://hdl.handle.net/10603/445877
dc.language	English
dc.publisher.institution	Department of Electronics and Communication Engineering
dc.publisher.place	Bhopal
dc.publisher.university	LNCT University
dc.relation
dc.rights	university
dc.source.university	University
dc.subject.keyword	Engineering
dc.subject.keyword	Engineering and Technology
dc.subject.keyword	Engineering Electrical and Electronic
dc.title	VLSI Implementation of 2D DCT Image Compression using Pipelined Architecture
dc.title.alternative
dc.type.degree	Ph.D.