Dynamically reconfigurable bit parallel pipelined embedded architecture for high speed signal processing

Abstract

A novel dynamically reconfigurable embedded architecture is newlineproposed in this thesis This architecture is targeted at applications involving newlineinherent data parallelism high regularity and high throughput Realtime newlinedigital signal processing systems are characterized by a large volume of realtime newlinedata input at variable rates and repetitive arithmetic operations on these newlinedata Solutions for such computational problems are mainly driven by the newlinedemanded speed flexibility in architecture and area budget available The newlineproposed architecture uses the concept of resource sharing and dynamic newlinereconfiguration newlineDynamically reconfigurable embedded architecture exploits the newlineconcept of resource sharing thereby achieving more functionality in less area newlinewithout execution time violation newline newline