Hardware architectures for accelerating convolution operations in convolutional neural network

dc.contributor.guide	Poddar, Soumyajit
dc.coverage.spatial
dc.creator.researcher	Hazarika, Anakhi
dc.date.accessioned	2022-12-20T04:33:09Z
dc.date.available	2022-12-20T04:33:09Z
dc.date.awarded	2022
dc.date.completed	2022
dc.date.registered	2016
dc.description.abstract	newline
dc.description.note
dc.format.accompanyingmaterial	DVD
dc.format.dimensions	29cm.
dc.format.extent	xx,137p.
dc.identifier.uri	http://hdl.handle.net/10603/428526
dc.language	English
dc.publisher.institution	Electronics and Communication Engineering
dc.publisher.place	Bongora
dc.publisher.university	Indian Institute of Information Technology Guwahati
dc.relation
dc.rights	university
dc.source.university	University
dc.subject.keyword	Engineering
dc.subject.keyword	Engineering and Technology
dc.subject.keyword	Engineering Electrical and Electronic
dc.subject.keyword	Hardware Accelerator, Convolutional Neural Network, FPGA, Approximate Computing, Machine Learning
dc.title	Hardware architectures for accelerating convolution operations in convolutional neural network
dc.title.alternative
dc.type.degree	Ph.D.