Design implementation and performance analysis of ternary CMOS logic circuits

Abstract

The evolution of an Integrated Circuit (IC) design, from Small Scale Integration (SSI), to the Very Large Scale Integration (VLSI), which currently has a millions of transistors in it, becomes the wider choice for any digital designer. Numerous circuit technologies have been used in this IC design evolvement drive. Predominantly, Metal Oxide Semiconductor (MOS) technology presented a number of key profits along with an effortless fabrication of basic transistor switch, ensuing in IC size reduction from time to time. Also, Complementary Metal Oxide Semiconductor (CMOS) technology modernized the semiconductor design applications by passing the low power consumption. Any Analog designs greatly rely on continuous signal response of transistors, whereas the digital designs rely on discrete-logic levels of the signals. Traditional, binary logic is the decoding method used deeply. But, the binary logic basically grips only two logic levels: 0 and 1. A further progress in this decoding is to make use of multiple levels i.e. more than two discrete-levels. Multiple-Valued Logic (MVL) circuits (Current 1994) propose a variety of impending openings for current VLSI circuit development. As detailed in Miller et al. (2007), MVL is considered as a discrete p-valued systems where pgt2, or to say, a non-binary-valued systems. In general, both binary-valued and discrete variables with an infinite number of values can be believed as MVL systems. newline