Optimization of motion estimation hardware using novel algorithmic approach for video compression
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Abstract
The Very Large-Scale Integration (VLSI) is an application of integrated circuits have increased in high-performance computing, consumer electronics and telecommunication at a very rapid pace. A video compression is the reduction of the quantity of data that is used for the representation of the video images. This is being used in real time and in video conference as well as the Motion Estimation (ME) based encoders are used in video compression techniques. The ME algorithm and its estimation are related to the speed of its coding and the ratio of compression and the quality of image of the decoded video. The ME is the movement of objects within a frame relating to the previous frame through that of the Motion Vectors (MV). The process of reconstruction of MVs is called Motion Compensation (MC). This approach is popularly employed for the determination of the MVs that is Block
newlineMatching (BM). The BM algorithms will decide the search points of search area as the candidate block locations for choosing the best matching block. The ME is the most computationally costly and resource hungry application in the process of compression and this is the reason for its highest activity and research interest over the last 20 years. This work deals with a Full Search Algorithm (FSA) and Four Step Search (FSS) algorithm for ME is proposed. In FSA, while searching exhaustively of the best matching to each candidate position, the correlation window is moved within the search. The best matching will be given through minimum dissimilarity. In FSS, the block distortion is measured with any of the cost function between the block in the current frame and the block to be searched for best match at the previous frame. If the minimum distortion point is at the center then the intermediate step of the algorithm may be skipped and it can move to final step.
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