Efficient hardware realizations of empirical mode decomposition and some other related algorithms for signal processing in real time

dc.contributor.guide	Pradhan, Sambhu Nath
dc.creator.researcher	Das, Kaushik
dc.date.accessioned	2024-02-06T08:49:42Z
dc.date.available	2024-02-06T08:49:42Z
dc.date.awarded	2023
dc.date.completed	2023
dc.date.registered	2017
dc.description.abstract	newlineThe thesis deals with the design and development of efficient hardware architectures for the real time computation of a few signal processing algorithms. Mainly this thesis focuses on the low cost and high speed hardware architecture design for the empirical mode decomposition (EMD), ensemble empirical mode decomposition (EEMD), And fast Fourier transform (FFT) algorithm. newline newline
dc.format.accompanyingmaterial	DVD
dc.identifier.uri	http://hdl.handle.net/10603/544092
dc.language	English
dc.publisher.institution	Department of Electronics and Communication Engineering
dc.publisher.place	Agartala
dc.publisher.university	National Institute of Technology Agartala
dc.rights	self
dc.source.university	University
dc.subject.keyword	Engineering and Technology
dc.subject.keyword	Engineering
dc.subject.keyword	Engineering Electrical and Electronic
dc.title	Efficient hardware realizations of empirical mode decomposition and some other related algorithms for signal processing in real time
dc.type.degree	Ph.D.