Analysis of Static Memory by Controlling Leakage Power

dc.contributor.guide	Balaji N and Padma Sai Y
dc.coverage.spatial
dc.creator.researcher	Surekha G
dc.date.accessioned	2025-01-13T06:20:34Z
dc.date.available	2025-01-13T06:20:34Z
dc.date.awarded	2022
dc.date.completed	2022
dc.date.registered	2012
dc.description.abstract	Attacked newline
dc.description.note
dc.format.accompanyingmaterial	DVD
dc.format.dimensions
dc.format.extent	117pp.
dc.identifier.researcherid
dc.identifier.uri	http://hdl.handle.net/10603/614373
dc.language	English
dc.publisher.institution	Department of Electronics and Communication Engineering
dc.publisher.place	Kukatpally
dc.publisher.university	Jawaharlal Nehru Technological University, Hyderabad
dc.relation
dc.rights	university
dc.source.university	University
dc.subject.keyword	Active Mode of Operation
dc.subject.keyword	Engineering
dc.subject.keyword	Engineering and Technology
dc.subject.keyword	Engineering Electrical and Electronic
dc.subject.keyword	Noise Margin
dc.subject.keyword	Operation of 6T SRAM Cell
dc.title	Analysis of Static Memory by Controlling Leakage Power
dc.title.alternative
dc.type.degree	Ph.D.