Power Minimization and Test Time Reduction in VLSI Circuits

Simple item page
dc.contributor.guideMadhavi B K
dc.coverage.spatial
dc.creator.researcherSreenivasula Goud Y
dc.date.accessioned2025-01-13T07:26:52Z
dc.date.available2025-01-13T07:26:52Z
dc.date.awarded2024
dc.date.completed2024
dc.date.registered2008
dc.description.abstractAttached
dc.description.note
dc.format.accompanyingmaterialDVD
dc.format.dimensions
dc.format.extent152pp.
dc.identifier.researcherid
dc.identifier.urihttp://hdl.handle.net/10603/614469
dc.languageEnglish
dc.publisher.institutionDepartment of Electronics and Communication Engineering
dc.publisher.placeKukatpally
dc.publisher.universityJawaharlal Nehru Technological University, Hyderabad
dc.relation
dc.rightsuniversity
dc.source.universityUniversity
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering Electrical and Electronic
dc.subject.keywordFault Analysis
dc.subject.keywordPower Minimization
dc.subject.keywordTest Time Reduction
dc.subject.keywordVLSI Circuits
dc.titlePower Minimization and Test Time Reduction in VLSI Circuits
dc.title.alternative
dc.type.degreePh.D.

Files

Original bundle

Now showing 1 - 5 of 13
Thumbnail Image
Name:
01_title.pdf
Size:
8.14 MB
Format:
Adobe Portable Document Format
Description:
Attached File
Download
Thumbnail Image
Name:
02_prelim pages.pdf
Size:
3.22 MB
Format:
Adobe Portable Document Format
Download
Thumbnail Image
Name:
03_contents.pdf
Size:
8.14 MB
Format:
Adobe Portable Document Format
Download
Thumbnail Image
Name:
04_abstract.pdf
Size:
8.14 MB
Format:
Adobe Portable Document Format
Download
Thumbnail Image
Name:
05_chapter_1.pdf
Size:
8.15 MB
Format:
Adobe Portable Document Format
Download

License bundle

Now showing 1 - 1 of 1
Thumbnail Image
Name:
license.txt
Size:
1.79 KB
Format:
Plain Text
Description:
Download

Collections

Department of Electronics and Communication Engineering