Implementation and verification of vedic fundamentals for concurrent architecture development

Abstract

In order to satisfy the standards of the market as well as the demands of newlinesociety, innovative and clever goods are conceived of and built using the most newlinerecent technology. The other side of the coin is that it is envisaged that such devices newlinewill be incredibly dependable, extremely quick, power efficient, affordable, and newlineportable. Due to the fact that standard integrated circuits are being used, it is no newlinelonger possible to achieve such characteristics. Complex Programmable Logic newlineDevices (CPLDs) and Field Programmable Gate Arrays (FPGAs), on the other newlinehand, are examples of microelectronics devices that have been introduced in recent newlineyears. These technologies have led to a substantial breakthrough in the processes of newlinedeveloping prototypes and products. It is now possible to finish the peculiarities of newlineapplications that are believed to be epic. This is because the advancements that newlinehave been made in the field of semiconductor manufacturing technology have made newlineit possible to develop microelectronic circuits that are completely unique. This newlinethesis is an introduction to the concurrent execution of Vedic principles for the newlineimplementation of multiplication. Specifically, the thesis focuses on the newlineimplementation of it. This is done in order to circumvent the possibilities of newlineoptimization for applications that are particularly complex. A method of calculating newlinethat dates back to ancient times is known as Vedic Mathematics (VM). A total of newlinesixteen sutras (Formulas) and thirteen upa-sutras (Sub-Formulas) have been newlineconsolidated into VM. Urdhav-Triyagbhyam, which is both vertical and crosswise, newlineis the formula that is utilized in the execution of multiplier architecture. This is the newlinecase out of all the offered formulae. newlineFundamentals of the Very High-Speed Integrated Circuit Hardware newlineDescription Language (VHDL) are utilized in the process of describing the newlinearchitecture throughout the development phase. In the following step, simulation is newlinecarried out for the goal of logic verification. Subsequently, th