Optimizing the Device Performance of Core Shell based Junction Less Field Effect Transistor

dc.contributor.guideAgarwal, Mohit
dc.coverage.spatial
dc.creator.researcherNarula, Vishal
dc.date.accessioned2022-12-08T12:27:58Z
dc.date.available2022-12-08T12:27:58Z
dc.date.awarded2022
dc.date.completed2022
dc.date.registered
dc.description.abstractThe miniaturization of dimensions of conventional metal oxide semiconductor field effect transistor (MOSFET) for improving the performance and higher transistor density has accompanied with short channel effects (SCE s). A rectangular core-shell based double gate junctionless transistor (RCS-DGJLT) has been introduced in this work in which an oppositely doped region known as rectangular core is sandwiched between the rectangular shells. For n- type RCS-DGJLT, the rectangular shells are doped with donor impurities and rectangular core is doped with acceptor impurities and vice a versa for p-type RCS-DGJLT. The RCS-DGJLT device is studied and optimized with design parameters such as shell thickness, core thickness, core doping, oxide thickness, channel length, etc. The optimization of RCS-DGJLT design parameters is investigated with the help of performance parameters such as OFF current (IOFF), ON current (ION), ON/OFF current ratio (ION/IOFF), threshold voltage, drain induced barrier lowering (DIBL), subthreshold slope (SS). The performance parameters of RCS-DGJLT are found to be excellent as compared to conventional DGJLT. The different device engineering has also been applied on the proposed RCS-DGJLT and performance parameters are compared with conventional DGJLT. The study includes Gate misalignment of bottom gate, Doping engineering in proposed device, Gate dielectric engineering, and Spacer dielectric engineering. The simulation study shows that RCS-DGJLT has provided a large tolerance limit to gate misalignment without affecting the performance of the device much unlike DGJLT. During the doping engineering, the different doping type and concentration is incorporated in various regions of RCS-DGJLT. It has been observed that either RCS-DGJLT with oppositely doped core architecture or RCS-DGJLT with oppositely doped core along with heavily doped source/drain extension has given outstanding performance parameters. The effect of gate dielectric in RCS-DGJLT is also explored and an interesting correlation is fou
dc.description.note
dc.format.accompanyingmaterialNone
dc.format.dimensions
dc.format.extentxxiii, 129p.
dc.identifier.urihttp://hdl.handle.net/10603/423227
dc.languageEnglish
dc.publisher.institutionDepartment of Electronics and Communication Engineering
dc.publisher.placePatiala
dc.publisher.universityThapar Institute of Engineering and Technology
dc.relation
dc.rightsuniversity
dc.source.universityUniversity
dc.subject.keywordCore-Shell Architecture
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering Electrical and Electronic
dc.subject.keywordJunction-Less MOSFET
dc.subject.keywordSemiconductors
dc.subject.keywordTransistor
dc.titleOptimizing the Device Performance of Core Shell based Junction Less Field Effect Transistor
dc.title.alternative
dc.type.degreePh.D.

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