VLSI design and hardware acceleration of speech coding algorithms using FPGA

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dc.contributor.guideChandel, Rajeevan
dc.coverage.spatial
dc.creator.researcherSingh, Dilip
dc.date.accessioned2024-10-28T09:11:13Z
dc.date.available2024-10-28T09:11:13Z
dc.date.awarded2024
dc.date.completed2024
dc.date.registered2018
dc.description.abstractnewline
dc.description.note
dc.format.accompanyingmaterialDVD
dc.format.dimensions
dc.format.extentxxviii, 173
dc.identifier.urihttp://hdl.handle.net/10603/598224
dc.languageEnglish
dc.publisher.institutionDepartment of Electronics and Communication Engineering
dc.publisher.placeHamirpur
dc.publisher.universityNational Institute of Technology Hamirpur
dc.relation
dc.rightsuniversity
dc.source.universityUniversity
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering Electrical and Electronic
dc.titleVLSI design and hardware acceleration of speech coding algorithms using FPGA
dc.title.alternative
dc.type.degreePh.D.

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