Certain investigations on different types of faults of a class of reed muller canonical circuits
| dc.contributor.guide | Ebenezer jeyakumar A | en_US |
| dc.coverage.spatial | faults of a class of reed muller canonical circuits | en_US |
| dc.creator.researcher | Neelakantan P N | en_US |
| dc.date.accessioned | 2014-10-13T09:30:42Z | |
| dc.date.available | 2014-10-13T09:30:42Z | |
| dc.date.awarded | 30/12/2011 | en_US |
| dc.date.completed | 01/12/2011 | en_US |
| dc.date.issued | 2014-10-13 | |
| dc.date.registered | n.d. | en_US |
| dc.description.abstract | Classically the solutions to the logic circuit design problems have newlinebeen obtained with the criteria to minimize the hardware complexity The newlinetesting problem was considered only after the design of the network was newlinecompleted But in modern designsor the past three decades the testability newlineaspects also have been included as an essential component of the design newlinespecifications itself Similarly while the main considerations in the early newlinedesigns were technology and mathematical tractability oriented only in newlinespecifying devices and structure the modern approaches or solutions will newlineadditionally have to consider the testability of the devices andor the network newlinestructure since the test sets ie the sets of test input patterns depend on the newlinenetwork topology and the devices used newline newline | en_US |
| dc.description.note | Reference p.141-147 | en_US |
| dc.format.accompanyingmaterial | None | en_US |
| dc.format.dimensions | 23cm | en_US |
| dc.format.extent | xxiii,150p. | en_US |
| dc.identifier.uri | http://hdl.handle.net/10603/26565 | |
| dc.language | English | en_US |
| dc.publisher.institution | Faculty of Electrical and Electronics Engineering | en_US |
| dc.publisher.place | Chennai | en_US |
| dc.publisher.university | Anna University | en_US |
| dc.relation | p.141-147 | en_US |
| dc.rights | university | en_US |
| dc.source.university | University | en_US |
| dc.subject.keyword | canonical circuits | en_US |
| dc.subject.keyword | electrical engineering | en_US |
| dc.subject.keyword | reed muller | en_US |
| dc.title | Certain investigations on different types of faults of a class of reed muller canonical circuits | en_US |
| dc.title.alternative | en_US | |
| dc.type.degree | Ph.D. | en_US |
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