Investigations on area efficient floating point arithmetic architectures

dc.contributor.guide	Ramesh, J
dc.coverage.spatial	Information and Communication Engineering
dc.creator.researcher	K, Thiruvenkadam
dc.date.accessioned	2019-03-19T05:23:21Z
dc.date.available	2019-03-19T05:23:21Z
dc.date.awarded	n.d.
dc.date.completed	2018
dc.date.registered	n.d.
dc.description.abstract	Abstract available
dc.description.note	Data not available
dc.format.accompanyingmaterial	None
dc.format.dimensions	30cm.
dc.format.extent	xxii, 119p.
dc.identifier.uri	http://hdl.handle.net/10603/232800
dc.language	Others
dc.publisher.institution	Faculty of Information and Communication Engineering
dc.publisher.place	Chennai
dc.publisher.university	Anna University
dc.relation	113-118
dc.rights	university
dc.source.university	University
dc.subject.keyword	DSP
dc.subject.keyword	Dynamicrange
dc.subject.keyword	Floatingpointarithmetic
dc.subject.keyword	Highperformance
dc.subject.keyword	VLSI
dc.title	Investigations on area efficient floating point arithmetic architectures
dc.title.alternative
dc.type.degree	Ph.D.