A Machine Learning Approach for Network on Chip Architecture Design

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dc.contributor.guideChakrabarti, Indrajit and Chattopadhyay, Santanu
dc.coverage.spatial
dc.creator.researcherSambangi, Ramesh
dc.date.accessioned2024-09-26T08:46:08Z
dc.date.available2024-09-26T08:46:08Z
dc.date.awarded2024
dc.date.completed2024
dc.date.registered
dc.description.abstractnewline
dc.description.note
dc.format.accompanyingmaterialDVD
dc.format.dimensions
dc.format.extent
dc.identifier.urihttp://hdl.handle.net/10603/591765
dc.languageEnglish
dc.publisher.institutionElectronics and Electrical Communication Engg
dc.publisher.placeKharagpur
dc.publisher.universityIndian Institute of Technology Kharagpur
dc.relation
dc.rightsuniversity
dc.source.universityUniversity
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering Electrical and Electronic
dc.titleA Machine Learning Approach for Network on Chip Architecture Design
dc.title.alternative
dc.type.degreePh.D.

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