design of n n reversible logic circuit with optimization for low power applications

dc.contributor.guide	Dr.K.VIDHYA
dc.coverage.spatial
dc.creator.researcher	KANNAN. R
dc.date.accessioned	2026-02-04T11:27:26Z
dc.date.available	2026-02-04T11:27:26Z
dc.date.awarded	2025
dc.date.completed	2025
dc.date.registered	2018
dc.description.abstract	newline
dc.description.note
dc.format.accompanyingmaterial	None
dc.format.dimensions
dc.format.extent
dc.identifier.researcherid
dc.identifier.uri	http://hdl.handle.net/10603/692532
dc.language	English
dc.publisher.institution	Department of Engineering
dc.publisher.place	Chennai
dc.publisher.university	Saveetha University
dc.relation
dc.rights	university
dc.source.university	University
dc.subject.keyword	Engineering
dc.subject.keyword	Engineering and Technology
dc.subject.keyword	Engineering Electrical and Electronic
dc.title	design of n n reversible logic circuit with optimization for low power applications
dc.title.alternative
dc.type.degree	Ph.D.