Low power SIC X filling TPG for multi model fault coverage using scan based BIST

dc.contributor.guide	Rao, Malleswara V
dc.coverage.spatial	Electronics and Communication Engineering
dc.creator.researcher	Hussain, M Mohammed Sabir
dc.date.accessioned	2019-09-19T04:49:23Z
dc.date.available	2019-09-19T04:49:23Z
dc.date.awarded	nd
dc.date.completed	2018
dc.date.registered	nd
dc.description.abstract	available
dc.description.note	-
dc.format.accompanyingmaterial	None
dc.format.dimensions	-
dc.format.extent	-
dc.identifier.uri	http://hdl.handle.net/10603/258588
dc.language	English
dc.publisher.institution	Department of Electronics and Communication Engineering
dc.publisher.place	Visakhapatnam
dc.publisher.university	GITAM University
dc.relation	No. of references 66
dc.rights	university
dc.source.inflibnet	INFLIBNET
dc.subject.keyword	ATPG procedure
dc.subject.keyword	BIST controller
dc.subject.keyword	Digital circuits
dc.subject.keyword	Engineering and Technology,Engineering,Engineering Electrical and Electronic
dc.subject.keyword	Switching activity
dc.subject.keyword	VLSI design flow
dc.title	Low power SIC X filling TPG for multi model fault coverage using scan based BIST
dc.title.alternative
dc.type.degree	Ph.D.