Design of Parallel Memory Architecture For Memory Allocation In Embedded System

Abstract

Recently, embedded devices are playing a prominent role in digital signal processors, newlinemulti-core systems, and hybrid processors. The performance of embedded devices is purely newlinedependent on the memory allocation operations. Due to advancements in embedded newlinesystems technology, memory allocations have become an important platform for a wide newlinerange of computer vision applications. Several methods, like application-specific newlineintegrated circuits, are developed for memory allocation. However, they are not suitable newlinefor real-time processing on general-purpose memory processors Anyhow, several newlinecomputer vision applications require faster hardware with robust PMA, which can be newlineimplemented using embedded system technology. Furthermore, Parallel memory newlineallocation (PMA) is a key component in microprocessors, microcontrollers, embedded newlinesystem-based applications control systems, and streaming DAQ platforms. Thus, the newlineFPGA platforms need to implement faster memory processing elements to satisfy these newlineapplication requirements and to enhance the performance of these applications. newlinePMA among various resources plays a crucial role in meeting the high-performance newlinerequirements in these applications. The conventional methods were implemented with newlinestatic random-access memory (SRAM) prototypes, but they failed to meet the maximum newlinedata transfer speed. This work focuses on the implementation of error-correctable ternary newlinecontent-addressable memory (EC-TCAM)-based PMA systems with error-resilient newlineproperties, which can be capable of detecting and correcting errors during the parallel data newlineallocation. Further, the priority circuit is used to generate the different levels of priorities, newlinewhich helps to transfer the data between master and slave devices and vice-versa. Here, the newlinesynchronization issues generated during parallel reading and writing operations are newlineminimized using priority circuit-controlled crossbar switching. The simulation results newlineshow the proposed EC-TCAM based PMA resulted in superior performance as compared newlineto the conventional approaches in terms of hardware resource utilization parameters such newlineas slice registers, look up tables (LUTs), LUT-flip-flops (LUT-FFs), delay, and power newlineconsumption. Finally, the proposed PMA method utilized 310 slice registers, 235 LUTs, newline156 LUT-FFs, 0.793ns of path delay, and 0.065watts of power. newlineHowever, the conventional memory allocators failed to improve the speed requirements by newlinereducing the area, delay, and power metrics. Therefore, this work is also focused on the newlinedevelopment of a data management engine-based network on chip (DME-NoC) processor, newlinewhich improves the performance by adopting the parallel memory allocation (PMA) newlinecontroller. The proposed DME-NoC is made up of several modules, including main core newlinememory, main slave memory, an address generator for generating core and slave addresses, newlinePMA controllers for memory allocations, read-write syncing for controlling memory newlinereading and writing operations, and a NoC for determining the best path. newline