Improved Architecture for Floating Point Computation Unit

dc.contributor.guide	Ramakrishnan V.N
dc.coverage.spatial
dc.creator.researcher	Dhanabal R
dc.date.accessioned	2021-01-27T12:03:29Z
dc.date.available	2021-01-27T12:03:29Z
dc.date.awarded	2020
dc.date.completed	2020
dc.date.registered	2010
dc.description.abstract	newline
dc.description.note
dc.format.accompanyingmaterial	None
dc.format.dimensions
dc.format.extent	1-133
dc.identifier.uri	http://hdl.handle.net/10603/313343
dc.language	English
dc.publisher.institution	School of Electronic Engineering
dc.publisher.place	Vellore
dc.publisher.university	VIT University
dc.relation
dc.rights	university
dc.source.university	University
dc.subject.keyword	Computational complexity
dc.subject.keyword	Floating-point
dc.subject.keyword	Low Power
dc.title	Improved Architecture for Floating Point Computation Unit
dc.title.alternative
dc.type.degree	Ph.D.