An Analytical Approach to Design Energy Efficient Arithmetic Circuits for Error Tolerant Multimedia Applications

Abstract

Energy efficient computing systems are crucial for handling huge workloads of multimedia data and with-stand the technology scaling impediments. The multimedia applications have inherent error tolerance, which is regarded as an opportunity to leverage the accuracy of underlying operations. Approximate hardware for arithmetic operations is observed to be a promising solution to obtain energy efficiency with restricted resource budgets. newlineMost of the existing approximate arithmetic circuits belong to either the fail rare case or the fail small case along with overheads due to error detection and corrections. However, the energy savings of such circuits is not on par with the loss of accuracy. There is the scope of a reduction in energy consumption with similar accuracy levels, which is explored in this thesis. This thesis overcomes the challenges by designing energy efficient binary arithmetic circuits with the aid of the observations drawn from the analysis of binary arithmetic functions. This work proposes solutions for approximate adders, multipliers, sum-of-products circuits, product-of sums circuits, and multiply-accumulate units. Extensive evaluation of the proposed designs using standard metrics in terms of circuit performance and error behavior are presented; the applicability of proposed approximate designs in image processing and quality assessment are also illustrated. The proposed designs have the advantage of noteworthy energy error trade-off without any error detection/correction logic. newline