Design of Tunnel Field Effect Transistor for low power and high performance applications

Abstract

newline In the era of nanotechnology, the uninterrupted down-scaling of conventional MOSFET technology has been catering to the demands of semiconductor industry by providing improved IC newlinefunctionality in terms of speed, compactness and better electrical characteristics. However, further down-scaling at sub-nanometer regime also prompts short channel effects and undesirable newlineamount of leakage currents leading to imminent power crisis as static power consumption becomes immoderate. Further reductions in technology node lead to increased power dissipation, newlinewhile supply voltage can no longer be reduced due to MOSFETs SSavg limitation of 60 mV/dec newlineat room temperature. Therefore, new devices based on new conduction mechanism and architectures is the need of hour to overcome MOSFETs SS newlineavg limitation and enable supply voltage newlinescaling. In this context, the primary goal of this research has been to investigate the performance newlineof one such steep-slope device: the Tunnel Field Effect Transistor.