Design and Analysis of Variable Resolution Iterative Analog to Digital Converter

Abstract

State of the art embedded platforms have been getting evolved rapidly. Microcontrollers or systems on chip (SoC) need to meet selection criterias in diverse application domains, being programmable architectures. One of the important peripherals on these architectures is analog to digital converter (ADC). ADC converts analog signal into digital domain and make it processable for SoC. There are different types of ADCs available. Selection of particular ADC in certain application is decided by its suitability for that application by performance parameters, principle and signal specifications [1-5]. newlineA microcontroller or SoC may not be used for diverse applications being designed with a particular single type of ADC on its chip. Moreover, diverse applications demand different ADCs. For example, Successive Approximation Register (SAR) ADCs employed in applications where low power consumption, better resolution is in the demand. Integrating type ADCs used in the applications, demanding linearity and accuracy at the cost of speed while pipeline ADCs are used for power optimization and speed requirements. newlineResolution is one of the important specifications of ADC. It decides the accuracy of the binary output. Variety of analog signals (speech, video, sensors, etc.) applied to ADC require different resolution at the output. Single ADC architecture can produce the variable resolution digital ouput according to the requirement of accuracy. Variable resolution controls number of bit transitions in the binary output and limits the data rate. newlineReconfigurablity property increases the scalability of the peripheral/architecture. Parameters of ADC architecture can be reconfigured so as to be suitable for particular type of input analog signal. Nevertheless, ADC architecture can also be reconfigured for its multiple types. This is termed as architectural reconfigurability . newlineThe work, presented in the thesis is demonstrating the design of three different digital hardware architectures for dual slope, feedback pipeline and successive ap