A Light Weight Serial Communication Protocol for Point to Point Connectivity

Abstract

With the increasing computational complexity, hardware accelerators are finding lot of usage in improvising holistic system performance. The scalable multi-core processor architecture together with hardware accelerators is able to significantly boost up the system performance in high-speed computing. newlineSuch hardware accelerators require connectivity between the processor system and the accelerating hardware for communicating data and control signals. Depending on the system level requirement, a serial or a parallel interface can be defined between the processor system and hardware accelerator block. The light weight serial communication protocol described here can be used to establish high speed serial connectivity between the System-on-Chip and the hardware accelerator platform. newlineWith the new protocol, the author has observed 3X reduction in area and 1.4X gain in latency over the other serial communication protocols. Using serial communication channel, it is possible to reduce the overall system cost while maintaining data integrity. High Speed serial IOs with embedded transceiver blocks are used for serial communication. Communication using high speed serial IOs requires an initialization procedure to ensure integrated data transfer across the serial links. newlineA physical layer initialization protocol defines the link establishment steps required before the actual data transfer. The overhead associated with the serial link initialization depends on variety of factors including the type of encoding used for transferring data across the link, initialization steps which confirm that the link partners are ready to exchange data, channel bonding procedure to integrate multiple serial links to achieve higher bandwidth etc. In this work, I have discussed about a novel approach for initializing serial communication channel using 64B/66B encoding technique and a light weight channel bonding methodology to minimize the overall initialization latency while minimizing the logic area and static and dynamic power consumption.