Design of novel approximate multipliers for real time image processing applications

Abstract

Approximate computing, particularly in multimedia tasks like newlineimage processing, is being recognized as an emerging approach that newlinestrategically allows slight deviations in accuracy to achieve significant newlinereductions in design factors such as area overhead, latency, and power newlineconsumption. Considerable attention is being gained by this method among newlineresearchers due to its potential to enhance the efficiency of critical newlinecomponents in real-time applications, such as multipliers. This thesis aims to newlineconstruct area-efficient approximate multipliers by employing modified newlineapproximate compressors, decoding algorithms, and truncation strategies. newlineFirstly, a comprehensive survey of approximate multiplier architectures is newlinepresented, focusing on various 4:2 compressor models proposed in recent newlineyears. The approximate multiplier designs are evaluated by considering newlinecritical performance metrics such as hardware usage, power requirements, newlinelatency, and error metrics. newlineThis work focuses on developing area-efficient multipliers tailored newlinefor error-resilient applications, where design parameters can be minimized newlinewith only a slight compromise in performance precision. Two novel newlineapproximate multipliers have been proposed using modified 4:2 compressors, newlinefull adders, and sum-generating units. newline