Development and Analysis of Generalized Integrator Based Phase Locked Loops for Synchronization under Adverse Grid Scenarios

dc.contributor.guide	Misra,Banishree and Nayak,Byamakesh
dc.coverage.spatial
dc.creator.researcher	Tripathy,Poonam
dc.date.accessioned	2025-12-11T06:24:06Z
dc.date.available	2025-12-11T06:24:06Z
dc.date.awarded	2025
dc.date.completed	2025
dc.date.registered	2019
dc.description.abstract	newline Abstract is Available newline
dc.description.note	Bibliography p.174-186
dc.format.accompanyingmaterial	DVD
dc.format.dimensions
dc.format.extent	xviii,189p.
dc.identifier.researcherid
dc.identifier.uri	http://hdl.handle.net/10603/679900
dc.language	English
dc.publisher.institution	School of Electrical Engineering
dc.publisher.place	Bhubaneswar
dc.publisher.university	KIIT University
dc.relation	No. of references173
dc.rights	university
dc.source.university	University
dc.subject.keyword	Engineering
dc.subject.keyword	Engineering and Technology
dc.subject.keyword	Engineering Electrical and Electronic
dc.title	Development and Analysis of Generalized Integrator Based Phase Locked Loops for Synchronization under Adverse Grid Scenarios
dc.title.alternative
dc.type.degree	Ph.D.