Design of reconfigurable architecture for high performance turbo decoder

Abstract

In digital communication error correction codes are the essential components to ensure robust digital applications Turbo code is one of the most attractive near Shannon limit error correction codes One key feature associated with turbo code is iterative decoding process It enables the turbo code to achieve the outstanding performance with moderate complexity However iterative process leads to low decoding throughput In order to achieve high decoding throughput large computation units are instantiated for each soft input soft output decoder and this results high complexity and more power consumption But nowadays in contrast the growing market of newlinewireless portable devices insists the industry to focus on compact low power circuit implementations Hence there is a need for innovations on Very Large Scale Integration design of high speed Turbo Decoders that are both area and power efficient In this work an efficient VLSI architecture for turbo decoding is proposed The proposed reconfigurable architecture for turbo decoder is based on Max Log MAP algorithm with sliding window technique Max Log MAP algorithm offers a good compromise between performance and complexity Hence it is selected for the proposed work The sliding window technique provides efficient resource usage to the proposed architecture by dividing a block of input symbols into a number of sub blocks newline newline