Redundant Allocation For Semiconductor Integrated Circuits In Nano Systems

Abstract

newlineThe development of CMOS scaling down technology to the nanometer dimensions creates some unreliable problems of defects and faults which lead to the failure in the nano scaled device. Based on that, this research work investigated the cause and effect of physical defects which occur in CMOS switches. The causes are the radiations, changes in temperature, sudden changes in electrical signals etc. Due to which it produces the effect of permanent faults such as opens and shorts, and transient faults of single event upset in CMOS switches. So, the research work focused on the analysis of input and output behavior of kinds of faults which occur in P-type and N-type MOS transistors separately. To tolerate the faults, a fault tolerant design can be modelled by applying redundancy techniques. Also the reliability of the system can be improved by adding redundancy to the system. This research work configured logic circuit as the system. The redundancy methodologies are applied for that circuit to design the fault tolerant model at the switch level and gate level with the consideration of specific kind of faults. newlineFor the switch level fault tolerant design, a suitable redundancy methodology is applied for the configured logic circuit. With respect to the output behavior of the permanent faults of stuck open and stuck short condition in CMOS switches. The formulations of failure probability are derived for the device and circuit with non-redundant and redundant design. These formulations are further considered as a measure of reliability. Using the formulations, the reliability parameters have been calculated for the configured logic circuit with and without redundancy. The parameters of reliability and fault tolerance are analysed and compared for both non-redundant and redundant switch level design to achieve feasibility. newlineFor the gate level fault tolerant design, a suitable redundancy technique is applied for the configured logic circuit. The transient faults of single event upset has been considered to derive the analytical formulations of input signal error probabilities. With the use of reliability formulations, fault tolerance has been measured. The parameters of reliability and fault tolerance are analysed and compared for both non-redundant and redundant gate level design to achieve feasibility. newlineFinally, this research work has compared two levels of redundancy which gives a greater percentage of fault tolerance with the feasible reliability.