A low power delay product hybrid CMOS full adder design for chain and tree structures and its characterization

dc.contributor.guide	Zaveri, Mazad S
dc.coverage.spatial	Engineering
dc.creator.researcher	Mewada, Manan Rajanikant
dc.date.accessioned	2021-03-10T12:56:19Z
dc.date.available	2021-03-10T12:56:19Z
dc.date.awarded
dc.date.completed	2019
dc.date.registered
dc.description.abstract	file attached
dc.description.note	bibliography p.76-82
dc.format.accompanyingmaterial	None
dc.format.dimensions	-
dc.format.extent	110 p.
dc.identifier.uri	http://hdl.handle.net/10603/317951
dc.language	English
dc.publisher.institution	School of Engineering and Applied Science
dc.publisher.place	Ahmedabad
dc.publisher.university	Ahmedabad University
dc.relation	no. of references 50
dc.rights	university
dc.source.inflibnet	INFLIBNET
dc.subject.keyword	Arithmetic and Logic Unit
dc.subject.keyword	Engineering
dc.subject.keyword	Engineering and Technology
dc.subject.keyword	Instruments and Instrumentation
dc.subject.keyword	Portable electronic devices
dc.subject.keyword	Processors
dc.title	A low power delay product hybrid CMOS full adder design for chain and tree structures and its characterization
dc.title.alternative	-
dc.type.degree	Ph.D.