Certain investigations on design for testability using kip bond logic and transmission gates circuitry in BIST for low cost testing

Abstract

The reduction of power consumption in testing a digital circuit is a major phenomenon present nowadays in the silicon industry The testing for power consumption constitutes the major time overhead of production of any digital circuit The digital circuit is designed in such a way that it produces different outputs during normal and the testing mode The normal mode of operation consumes low power which is produced by the primary inputs These primary inputs make the circuit to switch on several gates and thereby produce the output of the circuit hence called the primary output But during the testing mode the circuit works with the test vectors applied at the primary input terminals which in turn produce the output which is stored using the Output Response Analyser ORA for further verification The main objective of this work is to design the test pattern generator using 22 nanometer strained silicon Complementary Metal Oxide Semiconductor CMOS technology and use it for testing Further adding with test pattern generator kip bond logic based on Null Convention Logic is designed to keep a particular portion of the circuit in idle during the testing process At last the best flip-flop design is made available for the design of Linear Feedback Shift Register LFSR so that the circuit can be tested with reduced time and reduced power consumption for the test per test clock per test vector This work is mainly focussed on creating kip bond logic to carry out the test process with the half of the circuit remains idle so that the testing power consumption is reduced This is achieved by the idle state of the inactive components which reduces power consumption during the test per test clock per test vector newline