Design methodology to optimize the speed and power of the ultra scaled CNTFET circuits

dc.contributor.guideMohana Sundaram K
dc.coverage.spatialDesign methodology to optimize the speed and power of the ultra scaled CNTFET circuits
dc.creator.researcherPrakash P
dc.date.accessioned2020-10-21T10:59:44Z
dc.date.available2020-10-21T10:59:44Z
dc.date.awarded2019
dc.date.completed2019
dc.date.registeredn.d.
dc.description.abstractPresently the battery life and high spectral efficiency are found to be a perennial problem in smartphones With the advancement in the technologies towards 5G it has become mandatory to meet these challenges before problems are aggravated Besides CNTFET technology is found to be a promising field of research that is recommended in this work to solve the problem of battery life A Carbon Nano Tube Field Effect Transistor CNTFET has become one of the strong nominees to substitute silicon by its contribution of low power performance In the first phase of the work an experimental investigation is conducted to find the most influencing parameter by multivariate regression analysis using Hybrid PSO technique for obtaining the maximum performance in CNTFET The main parameters that were taken into consideration were thickness of nanotube length of the tube number of nanotubes pitch diameter of the nanotube temperature number of bias points in gate number of bias points in drain and threshold voltage Among these parameters the most impacting parameter was examined CNTFETs have better threshold high current density and high electron mobility when compared to traditional CMOSFET The main advantage with CNTFET is that it minimizes the short channel effects of existing Nano scaled MOSFET with cylindrical channel structure Recent studies on CNTFET show that thermal and electronic characteristics of CNTFET change with respect to change in length diameter and gate properties newline
dc.description.note
dc.format.accompanyingmaterialNone
dc.format.dimensions21cm
dc.format.extentxviii,154p.
dc.identifier.urihttp://hdl.handle.net/10603/303694
dc.languageEnglish
dc.publisher.institutionFaculty of Information and Communication Engineering
dc.publisher.placeChennai
dc.publisher.universityAnna University
dc.relationp.136-153
dc.rightsuniversity
dc.source.universityUniversity
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering
dc.subject.keywordEngineering Electrical and Electronic
dc.subject.keywordCNTFET technology
dc.subject.keywordPerennial problem in smartphones
dc.subject.keywordNanotubes pitch diameter
dc.titleDesign methodology to optimize the speed and power of the ultra scaled CNTFET circuits
dc.title.alternative
dc.type.degreePh.D.

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