Certain investigations on voltage level up shifter for low power system on chip applications

Abstract

The advancement in the vlsi technology with the ability to integrate billion/trillion transistors in a chip enables to develop high-performance and portable systems for wireless communication, multimedia and gaming applications. the design of low-power system-on-chip plays a major role to build a complete system comprising of digital, analog and mixed signal circuits on a single chip. furthermore, the recent systems operate under battery-powered and demand energy optimized architectures with high-speed performance. the design of energy-efficient systems is accomplished by incorporating effective power optimization techniques. one of the most important methods among several low-power techniques is the differential voltage and frequency scaling (dvfs) which scales down the supply voltage and the operating frequency. however, the dvfs approach compromises on the speed performance of the system. since the supply voltage is a predominant factor for systemand#8223;s power consumption, the usage of multiple supply voltages (i.e. multi-vdd) for different subsystems in the soc achieves both high-speed and energy-efficient operation. in the multi-vdd technique, different subsystems are energized with supply voltages (low and high) based on the critical and non-critical time constraints. it requires an essential building block called voltage level shifter (vls) as an interfacing circuit to interconnect various voltage domains together. the design of enhanced voltage level shifters is encouraged with high-speed energy-optimized level conversion to adopt the multi-vdd method for the low power soc. the vls can perform level-up and level-down conversions that can be realized using buffer, cross-coupled (half-latch), current mirror and hybrid structures. newline