Efficient Implementation Techniques of Signal Processing Algorithms and Artificial Neural Networks in FPGA

Abstract

The implementation of Artificial Neural Networks (ANNs) on hardware has been an engaging newlineresearch topic across various application domains. The superior performance of hardware-based newlineneural networks has rendered them increasingly appealing. Field-Programmable Gate Arrays (FPGAs) are predominantly chosen due to their parallelism and reconfigurability. Current design methodologies primarily rely on MATLAB and Python software libraries for ANN implementation. However, these implementations are time-consuming for training and often fail to meet the processing speed demands of real-time applications. In our thesis, we propose an efficient design methodology to speed up the process of determining neural network architecture to achieve a specified function, thereby accelerating the implementation of ANNs on the FPGA platform. Our proposed ANN implementation methodology makes use of a new algorithm called Neural Network Design Parameters Extraction (NNDPE) that is built in C++ and runs on the opensource library Fast Artificial Neural Network. The NNDPE program dramatically decreases the time needed to train and extract ANN design parameters such as layer count, neuron count per newlinelayer, and weights. The proposed design process consists of two parts. During the first step, an newlineANN is trained to extract weights using the NNDPE program approach. The second phase involves newlineimplementing an ANN on an FPGA.Our design process focuses on both software and hardware implementations of ANNs. The software implementation involves the implementation of ANN architecture using C++, whereas the hardware implementation focuses on implementing ANNs on FPGA. Our proposed preprocessing technique speeds up the ANN training. We proposed a fully parallel digital architecture for the ANN-FPGA based direct demodulator. We implemented the architecture using the ANN topology derived from our proposed ANN-FPGA development methodology.We validated the proposed design methodology using three neural network architectures to realize:A linear function.