Certain investigations on reconfigurable power aware lfsr architecture

Abstract

In digital circuit, consumption of power plays a vital role. In digital VLSI circuit, flip flop is one of the important components which consume more power. In this regard, the proposed Linear Feedback Shift Register (LFSR) architecture concentrated to minimize the power utilization of the circuit by developing an alternate circuit which suits for the low power applications. The shift register minimizes the area and power utilization by changing the behaviour of the internal circuit. LFSR is a special type of shift register which is used in communication systems.It is used to generate pseudo random sequence. In order to overcome the limitations of the existing framework, the LFSR is reframed to improve the circuit performance. In phase 1, the optimized LFSR using low power technique is proposed to minimize power, area and delay. The minimized number of transistors provides better performance over the existing models in terms of area, power and delay. Here three different techniques are compared and the results are shown. The compared outcome demonstrates that the proposed technique suits in reducing the number of transistors there by completely minimize the circuit area. Moreover the use of customized logic drastically reduces the power in the entire circuit and is well suited for low power portable applications. The delay in the proposed arrangement has been enhanced and shows the methodology improvement yet not a delay of mere tradeoffs for power and area. Moreover, the modified proposed methods demonstrates the effectiveness and the performance with less area, less power, efficient and simple for VLSI hardware implementation. In phase 2, the LFSR is proposed by replacing the flip-flop with latches to perform optimization. The inclusion of latch in place of flip-flop with simple circuit boosts the overall performance of the circuit. At that point, LFSR is structured and its performance is calculated. It is seen as superior to the previous LFSR design. Dual pulse clock is another proposed work in this part. The