Design techniques for high performance DSP systems using FPGA
| dc.contributor.guide | Ramakrishnan S | |
| dc.coverage.spatial | Design techniques for high performance DSP systems using FPGA | |
| dc.creator.researcher | Seshadri R | |
| dc.date.accessioned | 2021-10-13T05:56:38Z | |
| dc.date.available | 2021-10-13T05:56:38Z | |
| dc.date.awarded | 2020 | |
| dc.date.completed | 2020 | |
| dc.date.registered | ||
| dc.description.abstract | The demand for digital signal processing optimized solutions grows drastically in the modern years, especially in the field of communication and modern signal processing circuits. The finite impulse response (FIR) and an Infinite Impulse Response (IIR) filters play a crucial role in the design of any complex signal processing system. newlineIn the first stage of the research work the efficient fast digital FIR and IIR filter is proposed. This work demonstrates the Moving Average (MA) FIR filters and the fast MA FIR filters using look-ahead method. The conventional IIR filters using combination of integrator and comb sections (CIC) method, and the fast IIR filters using look-ahead methods are discussed in detail. Altera EP4CE115F29C7 field-programmable gate array (FPGA) device using Quartus II 13.1 has been used to synthesis and implement these filters. The performance metrics like the number of Logic Elements (LEs) and power consumption are compared with the MA and fast MA FIR. Similar parameters are used to evaluate IIR filters. The look-ahead level 1 has 189.79 MHz performance, and the fast filter with level 2 has 199.96 MHz performance. In addition, with the MA FIR filters, an 8-tap MA FIR filter using CIC method has 166.09 MHz performance, the same filter using look-ahead with level 1 has 167.22 MHz performance, and the same filter using look-ahead with level 2 has 168.56 MHz performance. The proposed FIR and IIR filter is designed efficiently in terms of speed for the application of VLSI signal processing environment. newline newline | |
| dc.description.note | ||
| dc.format.accompanyingmaterial | None | |
| dc.format.dimensions | 21cm | |
| dc.format.extent | xiv, 134p. | |
| dc.identifier.uri | http://hdl.handle.net/10603/344399 | |
| dc.language | English | |
| dc.publisher.institution | Faculty of Information and Communication Engineering | |
| dc.publisher.place | Chennai | |
| dc.publisher.university | Anna University | |
| dc.relation | p.123-133 | |
| dc.rights | university | |
| dc.source.university | University | |
| dc.subject.keyword | Engineering and Technology | |
| dc.subject.keyword | Engineering | |
| dc.subject.keyword | Engineering Electrical and Electronic | |
| dc.subject.keyword | Digital Signal Processing Systems | |
| dc.subject.keyword | Field Programmable Gate Array | |
| dc.subject.keyword | Finite Impulse Response | |
| dc.subject.keyword | Infinite Impulse Response | |
| dc.title | Design techniques for high performance DSP systems using FPGA | |
| dc.title.alternative | ||
| dc.type.degree | Ph.D. |
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