Design and Analysis of AI Enhanced Hybrid PUF to Enhance Hardware Security

Abstract

Physically Unclonable Functions (PUFs) have emerged as a cornerstone of hardware security, addressing critical concerns in device authentication, integrity verification, and cryptographic security. These security primitives play a pivotal role in various domains, including Very Large-Scale Integration (VLSI) systems, embedded systems, Internet of Things (IoT), Industrial IoT (IIoT), blockchain technology, and cybersecurity. Given the increasing vulnerability of modern electronic systems to cyber threats, enhancing the reliability, uniqueness, and security of PUF architectures has become imperative. newlineThis research presents a series of innovative PUF designs aimed at improving hardware security while optimizing resource efficiency and robustness against attacks. The Shift Register-based Arbiter PUF (SR-APUF) demonstrated a uniqueness of 47.3%, a reliability rate of 95.7%, and passed the NIST 800-22 randomness test with an 87% success rate. To further enhance performance, the Linear Feedback Shift Register-based Dual Arbiter PUF (LFSR-DAPUF) was proposed, incorporating challenge obfuscation using SHA-256-based Pseudo-Random Number Generators (PRNGs) and One-Time Passwords (OTPs). Experimental results showed an improved uniqueness of 50.8% and a reliability of 97.1% with Majority Voting and Error Correction Codes (ECC), while also achieving a NIST randomness pass rate of up to 98%. newlineAddressing the need for efficient resource utilization, this research explored a novel Dual Arbiter PUF with a Digitally Controlled Metastability (DCM) based True Random Number Generator (TRNG). The proposed architecture demonstrated improved uniqueness (48.1%) and reliability (97.6%) but at the cost of increased hardware resource consumption. To mitigate this, a single APUF with DCM was proposed, reducing complexity while maintaining security. Further, a Configurable Arbiter PUF leveraging metastability induced by DCM enhanced entropy sources, ensuring a balance between hardware efficiency and unpredictability.