Efficient cache state dumping for post silicon processsor validation

dc.contributor.guide	Panda, Preeti Ranjan
dc.coverage.spatial	Amar Nath and Shashi Khosla School of Information Technology
dc.creator.researcher	Vishnoi, Anant
dc.date.accessioned	2025-03-21T05:49:21Z
dc.date.available	2025-03-21T05:49:21Z
dc.date.awarded	2010
dc.date.completed	2010
dc.date.registered
dc.description.abstract	newline
dc.description.note
dc.format.accompanyingmaterial	DVD
dc.format.dimensions
dc.format.extent
dc.identifier.researcherid
dc.identifier.uri	http://hdl.handle.net/10603/629116
dc.language	English
dc.publisher.institution	Amar Nath and Shashi Khosla School of Information Technology
dc.publisher.place	Delhi
dc.publisher.university	Indian Institute of Technology Delhi
dc.relation	TH3981
dc.rights	university
dc.source.university	University
dc.subject.keyword	Engineering
dc.subject.keyword	Engineering and Technology
dc.subject.keyword	Instruments and Instrumentation
dc.title	Efficient cache state dumping for post silicon processsor validation
dc.title.alternative
dc.type.degree	Ph.D.